This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.2000-032338, filed Feb. 9, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device (EEPROM) that can carry out a data reprogram operation, specifically, a data reprogram operation at every page.
2. Description of the Related Art
Conventionally, a byte type EEPROM (Electrically Erasable PROM) that can carry out a reprogram operation at every page is known (see W. Johnson et al, xe2x80x9cA 16 kb Electrically Erasable Nonvolatile Memoryxe2x80x9d, ISSCC Digest of Technical Papers, PP. 152-153, Feb. 1982). As shown in FIG. 11, one memory cell MC of this byte type EEPROM is connected to a bit line BL via one select transistor SG. The memory cell MC of the byte type EEPROM has a FLOTOX structure (Floating Gate Tunneling Oxide structure) in which a tunnel insulating film for a reprogram operation is formed in a part of a gate insulating film close to drain electrode. A control gate line CGL of the memory cell MC is commonly provided at every one byte memory cells. The control gate line CGL is selected by a select switch circuit S, thereby a data reprogram operation is carried out at every one byte.
On the other hand, a NAND type EEPROM (see F. Masuoka et al, xe2x80x9cA new Flash EEPROM cell using triple polysilicon technologyxe2x80x9d, IEDM Technical Digest, pp. 464-467, Dec. 1984) is suitable for reprogramming data at large scale compared to the byte type EEPROM.
As shown in FIG. 12, at the NAND type EEPROM, 16 memory cells MC0 to MC15 are serially connected. An one end of the serially connected 16 memory cells is connected to a bit line BL via a select gate transistor SG1 and an other end of the serially connected 16 memory cells is connected to a common source line SL via a select gate transistor SG2. The memory cell MC has a stacked gate structure in which a floating gate and a control gate are laminated. All of an insulating film under a lower surface of the floating gate is used as a tunneling insulation film. Electrons move between the floating gate and a channel region by FN (Fowler Nordheim) tunneling. The control gates of the 128 bytes memory cells in a row direction are commonly connected to control gate line (one of the gate control lines CGL0 to CGL15). In the NAND type EEPROM, a page buffer to which one page program data can be loaded is provided. Thereby a data program operation at every page can be carried out.
FIG. 13 shows timing diagrams of a data reprogram operation in the byte type EEPROM. In this case, timing diagrams of the data reprogram operation that can be carried out at an arbitrary unit of 1 to 32 byte(s) is shown. A chip enable signal /CE is set to Low level, thereby selecting the chip. When a write enable signal /WE is set to Low level, an address ADD and a data DATA that we want to reprogram are inputted to the chip at every byte. And then, after a page window period which is a constant time period, the reprogram operation which includes a data erase operation and a data program operation is automatically carried out.
In a case of the NAND type EEPROM, in generally, the number of the memory cells that should be erased is different from the number of the memory cells that should be programmed. The reprogram operation includes the data erase operation and the program operation. In other words, as shown in FIG. 14, the data erase operation is carried out at a NAND cell block unit. First of all, the chip enable signal /CE is set to Low level, thereby selecting the chip. After that, when a command latch enable signal CLE is set to High level and the write enable signal /WE is set to High level, a set up command for the block erase operation is inputted from a I/O terminal. Next, when an address latch enable signal ALE is set to High level and the write enable signal /WE is set to Low level, a block address which should be erased is serially inputted from the I/O terminal. And then, the command latch enable signal CLE is set to High level, the write enable signal is set to Low level and an erase execution command is inputted from the I/O terminal. Thereby the block erase operation is carried out. The block erase operation often includes an erase verify read operation which confirms an erase state.
After the block erase operation that is stated above, the data program operation to the erased block is carried out at a timing shown in FIG. 15. First of all, the chip enable signal /CE is set to Low level, thereby selecting the chip. After that, when the command latch enable signal CLE is set to High level and the write enable signal /WE is set to Low level, a set up command for the data program operation is inputted from the I/O terminal. Next, when the address latch enable signal ALE is set to High level and the write enable signal /WE is set to Low level, a page address which should be programmed is inputted from the I/O terminal. Continuously, the address latch enable signal ALE is set to Low level, the write enable signal /WE is set to Low level and one page data which should be programmed are inputted. And then, the command latch enable signal CLE is set to High level, the write enable signal /WE is set to Low level and a program execution command is inputted from the I/O terminal. Thereby the data program operation for a selected page is carried out. The data program operation often includes a program verify read which confirms a program state.
In order to store one bit data, the byte type EEPROM has two elements which are one memory cell and one select transistor. Therefore, the cell size of the byte type EEPROM can be larger and it may be hard to be large capacity and low-costed.
On the other hand, the NAND type EEPROM was developed in order to overcome the difficulties. In the NAND type EEPROM, two select transistors are provided for a plurality of memory cells (for example 16 memory cells). Therefore, a cell size in which one bit data is stored is much smaller than that of the byte type EEPROM. In a result, it is capable of be a large scale capacity and low-costed. Therefore, the NAND type EEPROM is suitable for a large scale file memory.
Nevertheless, it is necessary that the data erase operation and the data program operation are independently carried out at a date reprogram operation in the NAND type EEPROM. Because the number of the erased memory cells for a case of a normal erase is different from the number of the programmed memory cells for a case of a program in the NAND type EEPROM. Therefore, it is not easy to control the data reprogram operation. In addition, the control of the reprogram operation is more complex because a command input system is often used. For example, in the command input system, a continuous input operation that includes (1) an input of the program set up command, (2) an input of a page address, (3) an input of data and (4) an input of a program execution command must be provided. Furthermore, in the NAND type EEPROM, it is hard to carry out such a fast access as a NOR type EEPROM. Because a plurality of the memory cells are connected serially.
A data erase operation is not impossible in the NAND type EEPROM. However, when we use a conventional control method for the reprogram operation, a control of the reprogram operation will be still complex and non high speed access still remains.
An object of the present invention is to provide a nonvolatile semiconductor memory device capable of a reprogram operation at a page unit that is controlled easier.
To achieve the object of the present invention, a nonvolatile semiconductor memory device having a data reprogram mode comprises a memory cell array in which a plurality of memory cells are arranged in a matrix form, a page buffer storing one page data to be programmed to memory cells which are selected in accordance with a page address signal, an internal column address generating circuit for generating column addresses of the one page with inputting the page address signal in order to transfer the one data stored in the page buffer to the memory cells, a column decoder receiving the column addresses from the internal column address generating circuit, and a control circuit having a data reprogram mode which is a mode for erasing one page data stored in the memory cells which are selected in accordance with the page address signal and continuously programming the one page data stored in the page buffer to the memory cells which are selected.
It is desirable the reprogram mode includes a verify read operation for confirming a data of a programmed memory cell after programming the one page data.
Also, it is desirable that the control circuit resets the one page data stored in the page buffer in the absent of an input of next one page data to the page buffer within a predetermined period from the input of the one page data.
Also, it is desirable that the internal column address generating circuit is an address resistor for initialized by the control circuit and generating column addresses which are increased one by one.
The nonvolatile semiconductor memory device having a data reprogram mode may further comprises a select gate circuit transferring column address signals to the column decoder, the column address signals being one of the column addresses from the internal column address generating circuit at the data reprogram mode and column addresses inputted from an external nodes at a data read out mode.
Also, it is desirable that each of the memory cells of the one page has a control gate, a drain node and a source node, the control gates are connected commonly, each of the drain node is connected to a bit line via a first select transistor, each of the source node is connected to the source line via second select transistor.
A nonvolatile semiconductor memory device having a data reprogram mode comprises a memory cell array including a plurality of memory cells which are formed in a matrix form and a plurality of bit lines, a page buffer circuit storing one page data which should be programmed to memory cells, the page buffer circuit being connected to the plurality of the bit lines, column gates connected to the plurality of the bit lines via the page buffer circuit and selecting a predetermined number of the bit lines, a column decoder transforming column address to the column gates, a sense amplifier circuit for detecting and amplifying a data which is stored in the memory cell in the memory cell array and the sense amplifier circuit being connected to the column gates, a column address buffer circuit receiving page column address signals which are supplied to an external terminal, an internal column address signal generating circuit for generating column address signals at a data reprogram operation in order to load the one page data which are stored in the memory cells to the page buffer circuit, a select gate circuit selecting one of the column address signals which are generated at the internal column address signal generating circuit and the page column address signals which are latched in the page buffer circuit and transforming to the column decoder circuit ,and a control circuit for controlling the data reprogram mode at which all of data stored in the memory cells selected by the page column address signals are erased and continuously data loaded to the page buffer circuits are programmed to the memory cells which are erased.